The US Department of Energy (DOE) has awarded the Argonne National Laboratory $4 million to fund research into energy-efficient microchips.

Set to launch in 2024, the project will see researchers use atomic layer deposition (ALD) to redesign microchips allowing them to use considerably less energy than current chips.

chip wafers semiconductors.png
– Sebastian Moss

Funded by the Energy Efficient Scaling for Two Decades (EES2) program from the DOE’s Advanced Materials and Manufacturing Technologies Office, the project is expected to last two and a half years and will see Argonne partner with Stanford University in California, Northwestern University in Illinois, and Boise State University in Idaho.

ALD is a manufacturing technique that allows materials and films to be deposited in exact places, for example placing metals on top of metals, dielectrics on dielectrics, or any other combination. Using this process, scientists are hoping to stack the memory and logic layers on top of each other, closing the gap between the microprocessor and the memory chips, and potentially reducing energy usage by 90 percent.

“Computers today spend over 90 percent of their energy shuttling data back-and-forth between the memory and logic functions, which exist on separate chips,” said Jeffrey Elam, who founded and directs the ALD project and will be leading the research team.

“This limitation is known as the ‘von Neumann bottleneck.’ Energy used to move the data is wasted as heat. As computing demand grows, we must develop low-power transistors and microchips to overcome this bottleneck and prevent an energy crisis.”

He added that compute power consumption has become “an urgent problem” and said the DOE is "committed to finding energy-efficient solutions that will flatten the demand curve for electricity use by microelectronics.”