Samsung's Advanced Institute of Technology (SAIT) is set to open an R&D counterpart in Silicon Valley dedicated to AI chip design.
According to a report from Business Korea, the new research facility, dubbed the Advanced Processor Lab (APL), will mainly be tasked with developing next-generation semiconductors, with a specific focus on RISC-V chips.
RISC-V is an open standard instruction set architecture (ISA) based on established RISC principles, which is provided under open-source licenses that do not require fees.
Citing industry sources, Business Korea reported that the ultimate goal of the APL institute is to design AI chips for Samsung based on the RISC-V architecture, with the company having reportedly already established an internal task force to begin the research process.
The news comes a month after Samsung Electronics announced it had established the Samsung Semiconductor AGI Computing Lab to develop a new type of chip for the next iteration of artificial intelligence.
Set to be located in both the US and South Korea, the lab will be focused on designing semiconductors to meet the compute-intensive processing demands of artificial general intelligence (AGI).
In a LinkedIn post, CEO of Samsung Semiconductor, Kye Hyun Kyung, said the computing lab will initially focus its R&D efforts on developing chips for LLMs, with the development of chips for AGI to happen at a later date.
Earlier this month, the US government announced it would be awarding Samsung Electronics $6.4bn in direct funding under the US Chips and Science Act to support the development of the company’s $40bn semiconductor cluster across a number of locations in Texas.
Two semiconductor foundries producing 4nm and 2nm chips, an advanced packaging facility for high memory bandwidth, and a research and development facility will be constructed in the city of Taylor.
The investment will also be used to expand an existing Samsung site in Austin, supporting the production of fully depleted silicon-on-insulator (FD-SOI) process technologies, a process that allows for more efficient transistor control when compared to conventional bulk technologies.
